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NCV7361A Voltage Regulator with Integrated LIN Transceiver
The NCV7361A consists of a low drop voltage regulator, 5.0 V/50 mA and a LIN bus transceiver. The LIN transceiver is suitable for LIN bus systems compatible to "LIN-Protocol Specification" Rev. 1.3, 2.0 and SAE J2602. The combination of voltage regulator and bus transceiver make it ideal for a powerful and inexpensive cost effective slave node in a LIN Bus system.
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8 8 1 SO-8 D SUFFIX CASE 751 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week 7361A ALYW
* Operating Voltage VSUP = 5.5 to 18 V * Very Low Standby Current Consumption < 110 mA in Normal Mode *
(< 50 mA in Sleep Mode) LIN-Bus Transceiver: PNP-Bipolar Transistor Driver Slew Rate Control and Wave Shaping for Best EMC Behavior BUS Input Voltage -24 V to 30 V (Independent of VSUP) Wake-Up Via LIN Bus Baud Rate up to 20 kBaud Compatible to LIN Specification 1.3, 2.0 and SAE J2602 Compatible to ISO9141 Functions Wake-Up by LIN BUS and Startup Capable Independent of EN Voltage Level Linear Low Drop Voltage Regulator: Output Voltage 5.0 V "2% Output Current Max. 50 mA Output Current Limit Overtemperature Shutdown Reset Time 100 ms and Reset Threshold Voltage 4.65 V CMOS Compatible Interface to Microcontroller Load Dump Protected (40 V Peak) Resistant Against Transient Pulses According to ISO 7637 at Pin VSUP, BUS and EN NCV Prefix for Automotive and Other Applications Requiring Site and Change Control
PIN CONNECTIONS
VSUP 1 EN 2 GND 3 BUS 4 (Top View) 8 7 6 5 VOUT RESET TxD RxD
* *
* * * * *
ORDERING INFORMATION
Device NCV7361AD NCV7361ADR2 Package SO-8 SO-8 Shipping 98 Units / Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2005
1
March, 2005 - Rev. 0
Publication Order Number: NCV7361A/D
NCV7361A
VSUP Aux. Supply Bandgap VBG Control Amplifier + - IVAUX Adjustment POR UVR VSUP 4.65 V VOUT Current Limitation Reset Generator
VOUT
MR
RESET EN GND Thermal Protection VSUP TSHD Wake- Filter Rec-Filter Receiver OSC VOUT Mode Control Wake-Up Control Reset Timer
RxD
30 k Slew Rate Control TSHD Driver Control Filter MR
VOUT
BUS
TxD
MR = Master Reset TSHD = Thermal Shutdown VBG = Bandgap Voltage
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 Symbol VSUP EN GND BUS RxD TxD RESET VOUT Supply voltage. Enable input controls the regulator. Active high. Ground LIN bus line. Receive output (push-pull to VOUT). Transmit input (pullup-input to VOUT). Reset output, active low (pullup to VOUT). Regulator output 5.0 V/50 mA. Description
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ELECTRICAL SPECIFICATIONS All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings (in accordance with IEC 134) given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of
OPERATING CONDITIONS
Characteristic Supply Voltage Operating Ambient Temperature Junction Temperature Symbol VSUP TA TJ Min 5.25 -40 - Max 18 +125 +150 Unit V C C
these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Correct operating of the device can't be guaranteed if any of these limits are exceeded.
MAXIMUM RATINGS
Rating VSUP Symbol VSUP Condition - T v 500 ms BUS VBUS - T v 500 ms Difference VSUP-VOUT EN TxD, RxD, RESET EN, TxD, RxD, RESET Short Circuit of Pin VSUP and VOUT ESD Capability TxD Pin ESD Capability on All Other Pins Junction Temperature Storage Temperature Lead Temperature Soldering Reflow: (SMD styles only) VSUP-VOUT VINEN VIN IIN IINSH ESDBUSHB ESDHB TJ TSTG Tsld - - - - - Human Body Model, 100 pF via 1.5 kW Human Body Model, 100 pF via 1.5 kW - - 60 second maximum above 183C -5C/+0C allowable conditions Min -1.0 - -24 - -0.3 -0.3 -0.3 -25 -500 -1.0 -2.0 - -55 - Max 30 40 30 40 40 VSUP + 0.3 VOUT + 0.3 25 500 1.0 2.0 150 150 240 peak V V V mA mA kV kV C C C V Unit V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
THERMAL RATINGS
Parameter SO-8 Package Junction-to-T (psi-JL2, YJL2) (Note 3) ab Junction-to-Ambient (RqJA, qJA) 1. 1 oz copper, 54 mm2 copper area, 0.062" thick FR4. 2. 1 oz copper, 714 mm2 copper area, 0.062" thick FR4. 3. psi-JL2 temperature was made at foot of lead #2. Test Conditions Typical Value Min-Pad Board (Note 1) 48 183 1.0 in Pad Board (Note 2) 43 120 C/W C/W Units
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ELECTRICAL CHARACTERISTICS (5.25 V v VSUP v 18 V, -40C v TA v 125C unless otherwise noted)
Characteristic VSUP Supply Current with VOUT "No Load'' (Note 4) Supply Current, "Sleep Mode'' Thermal Shutdown (Note 5) Thermal Recovery (Note 5) VSUP Undervoltage Reset "OFF" VSUP Undervoltage Reset "ON" VSUP Undervoltage Hysteresis Operating Voltage VOUT Output Voltage VOUTt VOUTh VOUTl 5.5 V v VSUP v 18 V 0 < IOUT < 50 mA VSUP > 18 V IVOUT = 20 mA, VSUP = 3.3 V IVOUT = 50 mA, VSUP = 3.3 V Drop-Out Voltage (Note 6) VD = VSUP-VOUT V Output Current Load Capacity ENABLE (EN) Input Voltage Low Input Voltage High Hysteresis (Note 5) Pulldown Current VENL VENH VENHYS IpdEN - - - VEN > VENH VEN < VENL RESET Output Voltage Low VOL IOUT = 1.0 mA, VSUP > 5.5 V 10 kW RESET to VOUT VSUP = VOUT = 0.8 V Pullup Current RESET Threshold Master Reset Threshold (Note 5) Ipu VRES VMRes - Referred to VOUT, VSUP > 4.6 V - - - -500 4.5 3.0 - - -375 4.65 3.15 0.8 0.2 -250 4.8 3.3 V V mA V V -0.3 2.5 100 1.0 70 - - - 4.0 100 1.6 VSUP +0.3 - 7.0 130 V V mV mA mA VD IVOUT = 20 mA IVOUT = 50 mA IVOUT Cload 3.0 V < VSUP < 18 V VOUT = 0 V Reference Figure 35 4.90 4.90 - - - - 50 4.7 5.0 5.0 VSUP-VD VSUP-VD - - - - 5.10 5.25 - - 150 500 150 - V V V V mV mV mA mF ISnl ISsleep TJSHD TJrec VSUVR_OFF VSUVR_ON VSUVR_HYS VSUP VEN = VSUP = 12 V, VBUS > VSUP - 0.5 V, Pins 5 to 8 Open VSUP = 12 V, VEN = 0 V, VBUS > VSUP - 0.5 V - - VSUP Ramp Up VSUP Ramp Down VSUVR_OFF - VSUVR_ON - - 155 126 - - 0.2 5.25 - 35 - - 3.5 3.0 - 12 110 50 175 130 3.9 3.3 - 18 mA mA C C V V V V Symbol Condition Min Typ Max Unit
4. See Figure 6 for test setup. 5. Not production tested, guaranteed by design and qualification. 6. Measured when the output voltage has dropped 100 mV from the VSUP = 12 V nominal value.
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ELECTRICAL CHARACTERISTICS (5.25 V v VSUP v 18 V, -40C v TA v 125C unless otherwise noted)
Characteristic LIN BUS INTERFACE Receive Threshold Receive Center Point Vthr_cnt = (Vthr_rec + Vthr_dom)/2 Receive Hysteresis Vthr_hys = Vthr_rec - Vthr_dom BUS Input Current (Recessive) (Note 7) BUS Input Current (Recessive) BUS Input Current (Recessive) BUS Pullup Resistor BUS Output Voltage (Dominant) (Note 7) BUS Output Voltage (Recessive) (Notes 7 and 8) BUS Current Limit TxD Pullup Resistance Input Low Level Input High Level RxD Output Voltage Low Output Voltage High VOL VOH IOUT = 1.0 mA IOUT = -1.0 mA - 4.2 - - 0.8 - V V Rpu_TxD VIL VIH - - - 9.5 - 3.75 15 - - 21 1.25 - kW V V Vthr_rec, Vthr_dom Vthr_cnt Vthr_hys IINBUSR -IINBUSR -IINBUSR RBUSpu VBUSdom VBUSrec ILIM 8.0 v VBUS v 18 V, VSUP = VBUS - 0.7 V, TxD = 4.5 V VSUP = 0 V, VBUS = -12 V VSUP = Open, VBUS = -18 V - 7.0 v VSUP v 18 V, TxD = 0 V, RL = 500 W 7.0 v VSUP v 18 V, TxD = 4.5 V VBUS > 2.5 V, TxD = 0 V 7.0 V v VSUP v 18 V 0.4 *VSUP 0.475 *VSUP 0.12 *VSUP - -1.0 -1.0 20 - 0.8 *VSUP 40 - 0.5 *VSUP 0.135 *VSUP - - - 30 - - - 0.6 *VSUP 0.525 *VSUP 0.15 *VSUP 20 - - 47 1.2 - 120 mA mA mA kW V V mA V Symbol Condition Min Typ Max Unit
7. See Figures 7, 8, and 9 for test setup. 8. The recessive voltage on BUS should not be less than 80% direct battery. The LIN specification requires an external reverse battery diode between the battery and VSUP. VSUP = VBAT -0.7 V.
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ELECTRICAL CHARACTERISTICS (7.0 V v VSUP v 18 V, -40C v TA v 125C unless otherwise noted)
Characteristic RESET AC CHARACTERISTICS Reset Time Reset Rise Time (Note 9) BUS Debounce Time (Note 14) Wake-Up Time tRes trr tdeb_BUS tWake_BUS - - - - 70 3.0 1.5 25 100 7.5 2.8 60 140 15 4.0 120 ms ms ms ms Symbol Condition Min Typ Max Unit
GENERAL LIN BUS INTERFACE AC CHARACTERISTICS Transmit Propagation Delay TxD -> BUS (Notes 10 and 11) tdr_TxD, tdf_TxD RL/CL at BUS 1.0 kW/1.0 nF 660 W/6.8 nF 500 W/10 nF VSUPMIN = 8 V tdr_TxD - tdf_TxD VSUPMIN = 8 V CL(RxD) = 50 pF VSUPMIN = 8 V tdr_RxD - tdf_RxD VSUPMIN = 8 V 20% v VBUS v 80% CL = 1.0 nF, RL = 1.0 kW VSUPMIN = 8 V 20% v VBUS v 80% CL = 1.0 nF, RL = 1.0 kW VSUPMIN = 8 V - - 4.0 ms
Symmetry of Propagation Delay BUS -> RxD (Note 10) Receiver Propagation Delay BUS -> RxD (Notes 10 and 11) Symmetry of Propagation Delay TxD -> BUS (Note 10) Slew Rate BUS Rising Edge (Note 9)
tdsym_TxD tdr_RxD tdf_RxD tdsym_RxD dV/dTrise
-2.0 - -2.0 1.0
- - - 1.7
2.0 6.0 2.0 2.5
ms ms ms V/ms
Slew Rate BUS Falling Edge (Note 9)
dV/dTfall
-2.5
-1.7
-1.0
V/ms
LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 1.3 Slope Time, Transition from Recessive to Dominant (Notes 11 and 12) Slope Time, Transition from Dominant to Recessive (Notes 11 and 13) Slope Time Symmetry tsdom tsrec tssym VSUP = 8.0 V RL = 500 W/CL = 10 nF VSUP = 8.0 V RL = 500 W/CL = 10 nF VSUP = 8.0 V RL = 500 W/CL = 10 nF Tssym = tsdom - tsrec VSUP = 18 V RL = 500 W/CL = 10 nF VSUP = 18 V RL = 500 W/CL = 10 nF VSUP = 18 V RL = 500 W/CL = 10 nF Tssym = tsdom - tsrec - - -7.0 - - - 12 12 1.0 ms ms ms
Slope Time, Transition from Recessive to Dominant (Notes 11 and 12) Slope Time, Transition from Dominant to Recessive (Notes 11 and 13) Slope Time Symmetry
tsdom tsrec tssym
- - -5.0
- - -
18 18 5.0
ms ms ms
9. Not production tested, guaranteed by design and qualification. 10. See Figures 2 and 3, Timing Diagrams. 11. See Figures 5, 6, 7, 8, and 9 for test setup. 12. tsdom = (tVBUS40% - tVBUS95%) / 0.55. 13. tsdom = (tVBUS60% - tVBUS5%) / 0.55. 14. See Figure 18.
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ELECTRICAL CHARACTERISTICS ( VSUP = 7.0 V to 18 V; BUS loads: 1.0 k / 1 nF; 660 / 6.8 nF; 500 / 10 nF, TxD Signal:
tBit = 50 ms, twH = TwL = tBit; trise = tfall < 100 ns, -40C TA 125C unless otherwise noted) Characteristic Symbol Condition Min Typ Max Unit
LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 2.0 Minimal Recessive Bit Time (Notes 15 and 16) Maximum Recessive Bit Time (Notes 15 and 16) Duty Cycle 1 Duty Cycle 2 15. See Timing Diagrams. 16. See Test Circuits for Dynamic and Static Characteristics. trec(min) trec(max) D1 D2 - - D1 = trec(min) / (2 * tBit) D2 = trec(max) / (2 * tBit) 40 40 0.396 - 50 50 - - 58 58 - 0.581 ms ms
TIMING DIAGRAMS
TxD
50%
tdf_TxD VBUS 95% 100%
tdr_TxD
BUS
50%
50%
5% 0% tdf_RxD RxD 50% tdr_RxD
Figure 2. Timing Diagram for Propagation Delay According to LIN 1.3 and 2.0
VBUS
100% 95%
60% BUS 40%
5% 0% tsdom Vdom tsrec
Figure 3. Timing Diagram for Slope Times According to LIN 1.3
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tBIT tBIT
TxD
tdom(max) VSUP 100%
trec(min)
tdom(min) BUS 58.1%
74.4% 58.1% 42.2% 28.4%
28.4% VSS 0%
trec(max)
RxD
Figure 4. Timing Diagram for Duty Cycle According to LIN 2.0
TEST CIRCUITS
NCV7361A
VSUP VSUP EN RL GND BUS VOUT RESET TxD RxD 10 mF + 100 nF
50 pF CL
Figure 5. Test Circuit for Delay Time, Slope Time, and Duty Cycle
12 V
IS1 A
NCV7361A
VSUP EN VOUT RESET TxD RxD 10 mF + 100 nF
+
GND BUS
Figure 6. Test Circuit for Supply Current ISnl
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NCV7361A
TEST CIRCUITS (continued)
NCV7361A
VBAT VSUP EN GND V VBUSREC BUS VOUT RESET TxD RxD 10 mF + 100 nF
Figure 7. Test Circuit for Bus Voltage "Recessive'' (VBUSREC)
NCV7361A
VSUP VSUP EN 500 GND BUS V VBUSD TxD RxD VOUT RESET 10 mF + 100 nF
Figure 8. Test Circuit for Bus Voltage "Dominant'' VBUSDOM
NCV7361A
VBAT VSUP EN IINBUSR A GND BUS VOUT RESET TxD RxD 10 mF + 100 nF
Figure 9. Test Circuit for Bus Current "Recessive'' IINBUSR
NCV7361A
13.5 V VSUP EN GND BUS VOUT RESET TxD RxD CVAR + 100 nF RL V VOUT
Figure 10. Test Circuit for VOUT Rise Time vs. Load Capacitance and Resistance
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TYPICAL OPERATING CHARACTERISTICS
Figure 11. Vout Rise Time with 1 mF, 10 mF, 100 mF, and 150 mF Capacitors and 200 W Load using EN to Enable the Output.
Figure 12. Vout Rise Time with a 10 mF Load Capacitor and 1 kW, 200 W, and 100 W Load using EN to Enable the Output.
Figure 13. Vout Rise Time with a 100 mF Load Capacitor and 1 kW, 200 W, and 100 W Load using EN to Enable the Output.
Figure 14. Vout Rise Time with a 150 mF Load Capacitor and 1 kW, 200 W, and 100 W Load using EN to Enable the Output.
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NCV7361A
FUNCTIONAL DESCRIPTION The NCV7361A consists of a low drop voltage regulator 5.0 V/50 mA and a LIN Bus transceiver, which is a bidirectional bus interface for data transfer between the LIN bus and the LIN protocol controller. Additionally, the NCV7361A features a RESET output with a reset delay of 100 ms and a fixed threshold of 4.65 V and Enable (EN) control for the regulator.
Operating Modes
The NCV7361A provides two main operating modes "normal" and "sleep" and the intermediate states "POR", "Ini-state" and "thermal shutdown". The main modes are fixed states defined by basic actions (VSUP start, EN or wake-up). The intermediate states are soft states. They aren't defined by logical actions but by changes of voltage (VSUP, VOUT) or junction temperature.
VSUP POWER ON
Clear All State-FF Clear RESET Timer Regulator ON VOUT Ramp Up RESET = L Wake-Up Disabled Ini-state VSUP < UVR_ON VOUT > VRES (4.65 V)
VOUT < VRES
POR
VSUP > UVR_OFF
VSUP < UVR_ON
EN = H Regulator ON RESET = L after 100 ms RESET = H Wake-Up Disabled LIN Transceiver ON
VSUP > UVR_OFF and (EN = L/H or Bus Wake-Up)
Normal Mode
EN = H/L EN = L Sleep Mode Sleep Mode and TJ < TJREC
Sleep Mode and TJ < TJSHD
Normal Mode and TJ < TJREC
Normal Mode and TJ > TJSHD
Regulator OFF Wake-Up Enabled (LIN Receiver ON) LIN Transmitter OFF TJ < TJREC
Thermal Shutdown
Regulator OFF Wake-Up Disabled LIN Transceiver OFF
Figure 15. State Diagram of Operating Modes Normal Mode Sleep Mode
The whole NCV7361A is active. Switching to normal mode can be done via the following actions: * Start of VSUP or after Undervoltage Reset * Rising Edge at EN (EN = High) (Local Wake-Up) * Activity on the LIN Bus (Remote Wake-Up)
Sleep mode is most current saving. With a falling edge on EN (EN = Low) the NCV7361A is switched from normal mode into sleep mode. The voltage regulator will be switched off and the LIN transceiver is in recessive state.
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NCV7361A
VSUP
VSUVR_OFF VSUVR_ON
UVR
POR
EN = H/L
POR
UVR
Normal Mode
Sleep Mode
Normal Mode
VOUT Figure 16. Operating of Power On and Undervoltage RESET
Switching into sleep mode can be done independently from the current transceiver state. That means if the transmitter is in dominant state this state will be cancelled and it will be switched to recessive state.
POR-state
This is the power-on-reset state of the NCV7361A, while VSUP < VSUVR_OFF. If the prior state was sleep mode, the NCV7361A switches via the Ini-state to normal mode.
Ini-state
This is an intermediate state, which will pass through after switch-on of VSUP or VOUT. The NCV7361A remains in this state if VOUT is below VRES (Reset Output = L) and VSUP > VSUVR_ON.
Thermal Shutdown
independence from the rise time of VSUP. During fast VSUP edges the Power-on-Reset will be active. If the increasing of VSUP is very slow (> 1 ms/V) the undervoltage reset unit initializes the voltage regulator if VSUP > VSUVR_OFF (typical 3.5 V). The effects of both POR circuits at different VSUP slopes as shown in Figure 16. After POR the voltage regulator starts and VOUT will be output. If VOUT > VMRes the bus interface will be activated. If the VOUT voltage level is higher than VRES, the reset time tRes = 100 ms is started. After tRes the RESET output switches from low to high (Figure 16).
Start of Linear Regulator via Wake-Up
If the junction temperature TJ is higher than TJSHD (>155C), the NCV7361A will be switched into the thermal shutdown mode. The behavior within this mode is comparable with the sleep mode except for LIN transceiver operating. The transceiver is completely disabled, no wake-up functionality is available. If TJ falls below the thermal recovery temperature TJREC (typical 140C) the NCV7361A will be recover to the previous state (normal or sleep).
Initialization
The initialization is only being done for the VOUT circuitry parts. This procedure begins with leaving the master reset state (VOUT > VMRes) and runs in the same manner as the VSUP - Power-On.
Wake-Up
If the regulator is put into sleep mode it can be "waked-up" with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of minimum 60 ms switches on the regulator. After the BUS has "waked-up" the regulator, it can only be switched off with a high level followed by a low level on the EN pin.
VSUP Undervoltage Reset
Initialization is started if the power supply is switched on as well as every rising edge on of the NCV7361A via the EN pin.
VSUP - Power On
If VSUP is switched on the NCV7361A starts to normal mode via the POR- and Ini-state. A combination of dynamic POR and undervoltage reset circuitry generates a POR signal, which switches the NCV7361A into normal mode. This power on behavior is independent from the status of the EN pin. Power-on-Reset and undervoltage reset operates independent from each other, which secures the
The undervoltage detection unit inhibit an undefined behavior of the NCV7361A under low voltage condition. If VSUP drops below VSUVR_ON (typical 3 V) the undervoltage detection becomes active and the IC will be switched to POR state. The following increasing of VSUP above VSUVR_OFF (typical 3.5 V) cancels this POR state and the voltage regulator starts with the initialization sequence.
VSUP Undervoltage in Normal Mode
Supply Voltages below VSUVR_OFF do not influence the voltage regulator. The output voltage VOUT follows VSUP.
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VSUP Undervoltage in Sleep Mode LIN BUS Transceiver
No exit from the sleep mode will take place if the VSUP voltage drops down to VSUVR_ON (typical 3.0 V). The undervoltage reset becomes active (POR-state). As a result of this operating, the sleep mode is left to the normal mode. If VSUP rises again above VSUVR_OFF (typical 3.5 V), the IC initializes the voltage regulator and continues to work with the normal mode. The undervoltage reset unit secures stable operating in the undervoltage range of VSUP down to GND level. The dynamic Power-On-Reset secures a defined internal state independent from the duration of the VSUP drop, which secures a stable restart.
Overtemperature Shutdown
The NCV7361A is a bidirectional bus interface device for data transfer between the LIN bus and the LIN protocol controller. The transceiver consists of a pnp-driver (1.2 V @ 40 mA) with slew rate control, wave shaping and current limit, and a high voltage receiver/comparator followed by a filter circuit.
Transmit Mode
If the junction temperature is 155C < TJ < 170C the overtemperature recognition will be activated and the regulator voltage will be switched off. The VOUT voltage drops down, the reset state is entered and the bus-transceiver is switched off (recessive state). After TJ falls below 140C the NCV7361A will be initialized again (Figure 17) independently from the voltage levels on EN and BUS. Within the thermal shutdown mode the transceiver can not be switched to the normal mode neither with local nor with remote wake-up. The operation of the NCV7361A is possible between TAmax (125C) and the switch-off temperature, but small parameter differences can appear. After overtemperature switch-off the IC behaves as described in Figure 17.
During transmission the data at the TxD pin will be transferred to the BUS driver for generating a BUS signal. To minimize the electromagnetic emission of the bus line, the BUS driver has integrated slew rate control and wave shaping circuitry. Transmitting will be interrupted in the following cases: * Sleep Mode * Thermal Shutdown Active * Master Reset (VOUT < 3.15 V) The recessive BUS level is generated from the integrated 30 k pullup resistor in series with a diode This diode prevents reverse current on VBUS when VBUS > VSUP. No additional termination resistor is necessary to use the NCV7361A in LIN slave nodes. If this IC is used for LIN master nodes, it is necessary to terminate the bus pin with an external 1.0 kW resistor in series with a diode to VBAT.
Receive Mode
The data signal from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus are suppressed by the internal filter circuit (t = 2.8 ms).
VSUP
T>TJ VOUT VRES
TtRes
trr
tRes
tRes
tRes
RESET
Initialization
Thermal shutdown
Spike VSUP
Low voltage VSUP
Spike VCC
Current limitation active
Figure 17. RESET Behavior
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VSUP Vthr_max 60% BUS 50% 40% Vthr_min Vthr_hys Vthr_cnt
t < tdeb_BUS
t < tdeb_BUS
RxD
Figure 18. Receive Mode Impulse Diagram
The receive threshold values Vthr_max and Vthr_min are symmetrical to 0.5*VSUP with a hysteresis of 0.135*VSUP . The LIN specific receive threshold is between 0.4*VSUP and 0.6 * VSUP .
Data Rate
The constant slew rate principle holds appropriate voltage levels and can operate within the LIN Protocol Specification for RC oscillator systems with a matching tolerance up to "2% between 2 nodes.
TxD Input
The NCV7361A is a constant slew rate transceiver. The bus driver works with a fixed slew rate range of 1.0 V/ms v DV/DT v 2.5 V/ms. This principle provides good symmetry of the slope times between recessive to dominant and dominant to recessive slopes within the LIN bus load range (CBUS, Rterm). The NCV7361A guarantees data rates up to 20 kb within the complete bus load range under worst case conditions.
MCU VCC RPU_TxD
The 5.0 V input TxD directly controls the BUS level: TxD = low BUS = low (dominant level) TxD = high BUS = high (recessive level) The TxD pin has an internal pullup resistor connected to VOUT. This guarantees that an open TxD pin generates a recessive BUS level.
NCV7361A VOUT Typ. 15 k RC Filter (10 ns)
IPU_TxD
TxD
Figure 19. TxD Input Circuitry
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RxD Output
16 14 12 lol_RESET (mA) 10 8 6 4 2
RxD
The received BUS signal will be output to the 5.0 V RxD pin: BUS < Vthr_cnt - 0.5 * Vthr_hys RxD = low BUS > Vthr_cnt + 0.5 * Vthr_hys RxD = high This output is a push-pull driver between VOUT and GND with an output current capability of 1.0 mA.
NCV7361A VOUT MCU
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOUT (V)
Figure 22. Output Current of Reset Output vs. VOUT Voltage
Figure 20. RxD Output Circuitry
Initialization
The initialization is started if VSUP is switched on. This is independent of the EN pin.
VSUP Power ON
Linear Regulator
The NCV7361A has an integrated low dropout linear regulator with a P-Channel MOSFET output driver whose output is 5.0 V "2% at v50 mA and 5.5 V v VSUP v 18 V. Figure 21 shows typical current limit based on the output voltage.
120 100 80 60 40 20 0 0 1 2 3 VOUT (V) 4 5 6
IVOUT (mA)
The NCV7361A starts in the normal mode when VSUP is applied [>3.15 V (typical)]. The internal circuitry on VOUT as well as the internal regulator starts the initialization with power-on-reset. The voltage regulator is switched on. If VOUT > VPOR the bus-interface will be activated. If VOUT is higher than VRes, the reset time tRes = 100 ms is started. After tRes the RESET output switches from low to high (Figure 22). The initialization procedure at power on is started independent from the EN state. The regulator can only be turned off with a high level followed by a low level on the EN pin.
Mode Input EN
Figure 21. Characteristic of Current Limit vs. Output Voltage RESET
RESET switches from low to high if VSUP is switched on and VOUT > VRES for tRes. If VOUT drops below VRES, the RESET output goes from high to low after trr. Short transients will be filtered. The RESET output driver is driven from VOUT to guarantee proper operation.
The NCV7361A is switched into the sleep mode when EN goes from high to low. The normal mode will be kept as long as EN = high. The regulator can be turned off by switching EN high to low independent of the state of the bus-transceiver. The EN input is internally pulled down to guarantee a low with no connection. In the high state, the pulldown current will be switched off to reduce the quiescent current. The maximum input voltage is VSUP. The threshold is typical 2.1 V and therefore CMOS levels can be used as input signals. Figure 23 shows the internal circuitry of the EN pin. The EN input is internally pulled down to secure that if this pin is not connected a low level will be generated. It will be used two different pull down current sources for high and low level to minimize the sleep mode current.
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NCV7361A
The 4 mA pulldown current source is used if the input voltage VIN > high level voltage VENH. If the input voltage drops below the low level of EN VENL, the second current source is used. The resulting pulldown current in this case is 100 mA. The wide input voltage range allows different EN control possibilities. If the EN input is connected to an CMOS output of the MCU, a falling edge switches the NCV7361A into sleep mode (the regulator is also switched off). The wake-up is only possible via the bus line.
1000
VSUP
100
RIN_HL
RIN_LH
EN
4 mA
Voltage Limiter 96 mA
Enable
RIN (kW)
10
0 0 Figure 23. EN Input Circuitry 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIN (V)
Figure 24. RIN Characteristics of EN Input
MCU NCV7361A VBAT CIN + VSUP EN GND LIN-BUS 200p Cload BUS VOUT RESET TxD RxD + +5 V
Figure 25. EN Controlled via MCU
MCU NCV7361A VBAT CIN + VSUP EN GND LIN-BUS 200p Cload BUS VOUT RESET TxD RxD + +5 V
Figure 26. Permanent Normal Mode http://onsemi.com
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NCV7361A
If the application does not need the wake-up capability of the NCV7361A, a direct connection EN to VSUP is possible. In this case, the NCV7361A operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via a VBAT signal.
Wake-Up Overtemperature Shutdown
If the regulator is in a standby (sleep) mode, it can be woken up with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of minimum 25 ms switches on the regulator. After the BUS wake-up for the regulator, it can only be turned off with a high level followed by a low level on the EN pin.
The thermal shutdown threshold is 155C < TJ < 175C. When exceeded, the overtemperature shutdown will be active and the regulator voltage will be switched off. VOUT drops down, the reset state is entered and the bus-transceiver is switched off (recessive state). After TJ falls below 140C, the NCV7361A will be initialized (see Figure 17), independent from the voltage levels on EN and BUS. Within the thermal shutdown mode, the transceiver can't be switched to the normal mode with local or with remote wake-up. Function of the NCV7361A is possible between TAmax (125C) and the switch-off temperature, but small parameter differences can appear. After overtemperature switch-off the IC behaves as described in the RESET chapter.
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NCV7361A
APPLICATION HINTS
LIN System Parameter Bus Loading Requirements
Parameter Operating Voltage Range Voltage Drop of Reverse Protection Diode Voltage Drop at the Series Diode in Pull Up Path Battery Shift Voltage Ground Shift Voltage Master Termination Resistor Slave Termination Resistor Number of System Nodes Total Length of Bus Line Line Capacitance Capacitance of Master Node Capacitance of Slave Node Total Capacitance of the Bus including Slave and Master Capacitance Network Total Resistance Time Constant of Overall System Symbol VBAT VDrop_rev VSerDiode VShift_BAT VShift_GND Rmaster Rslave N LENBUS CLINE CMaster CSlave CBUS RNetwork t Min 8.0 0.4 0.4 0 0 900 20 2 - - - - 1.0 537 1.0 Typ - 0.7 0.7 - - 1000 30 - - 100 220 220 4.0 - - Max 18 1.0 1.0 0.1 0.1 1100 60 16 40 150 - 250 10 863 5.0 Unit V V V VBAT VBAT W kW - m pF/m pF pF nF W ms
Recommendations for System Design
The goal of the LIN physical layer standard is to have a universal definition of the LIN system for plug and play solutions in LIN networks up to 20 kbd bus speeds. In case of small and medium LIN networks, it's recommended to adjust the total network capacitance to at least 4.0 nF for good EMC and EMI behavior. This can be done by setting only the master node capacitance. The slave node capacitance should have a unit load of typically 220 pF for good EMC/EMI behavior. In large networks with long bus lines and the maximum number of nodes, some system parameters can exceed the defined limits and the LIN system designer must intervene. The whole capacitance of a slave node is not only the unit load capacitor itself. Additionally, there is the capacitance of wires and connectors, and the internal capacitance of the LIN transmitter. This internal capacitance is strongly dependent on the technology of the IC manufacturer and should be in the range of 30 pF to 150 pF. If the bus lines have a total length of nearly 40m, the total bus capacitance can exceed the LIN system limit of 10 nF. A second parameter of concern is the integrated slave termination resistor tolerance. If most of the slave nodes have a slave termination resistance near by the allowed maximum of 60 kW, the total network resistance is more
than 700 W. Even if the total network capacitance is below or equal to the maximum specified value of 10 nF, the network time constant is higher than 7.0 ms. This problem can be solved only by adjusting the master termination resistor to the required maximum network time constant of 5.0 ms (max). The LIN bus output driver of the NCV7361A provides a higher drive capability than necessary (40 mA @ 1.2 V) within the LIN standard (33.6 mA @ 1.2 V). With this driver stage the system designer can increase the maximum LIN networks with a total network capacitance of more than 10 nF. The total network resistance can be decreased to:
Rtl_min + (VBat_max * VBUSdom) IBUS_max + (18 V * 1.2 V) 40 mA + 420 W
NOTE: The NCV7361A meets the requirements for implementation in RC-based slave nodes. The LIN Protocol Specification requires the deviation of the slave node clock to the master node clock after synchronization must not differ by more than "2%. Setting the network time constant is necessary in large networks (primary resistance) and also in small networks (primary capacitance).
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NCV7361A
MIN/MAX SLOPE TIME CALCULATION
VBUS 100% 95%
60% BUS 40%
5% 0% tsdom Vdom tsrec
Figure 27. Slope Time Calculation
The slew rate of the bus voltage is measured between 40% and 60% of the output voltage swing (linear region). The output voltage swing is the difference between dominant and recessive bus voltage.
dV dt + 0.2 * Vswing (t40%-t60%)
50 45 40 35 PD (mW) 30 25 20 15 10 5 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSUP (V)
The slope time is the extension of the slew rate tangent until the upper and lower voltage swing limits:
tslope + 5 * (t40%-t60%)
The slope time of the recessive to dominant edge is directly determined by the slew rate control of the transmitter:
tslope + Vswing dV dt
The dominant to recessive edge is influenced from the network time constant and the slew rate control, because it's a passive edge. In case of low battery voltages and high bus loads the rising edge is only determined by the network. If the rising edge slew rate exceeds the value of the dominant one, the slew rate control determines the rising edge.
Power Dissipation and Operating Range
Figure 28. Power Dissipation LIN Transceiver @ 20 kbit
The permitted package power dissipation can be calculated:
T * TA PDmax + J RqJ-A
The max power dissipation depends on the thermal resistance of the package and the PCB, the temperature difference between Junction and Ambient as well as the airflow. The power dissipation can be calculated with:
PD + (VSUP * VOUT) * IVOUT ) PD_TX
If we consider that PD_TX_max = f(VSUP), it can be calculated the max output current IVOUT on VOUT:
TJ-TA
IVOUTmax + RqJ-A
* PD_TX_max @ VSUP VSUP * VOUT
The power dissipation of the transmitter PD_TX depends on the transceiver configuration and its parameters as well as on the bus voltage VBUS = VBAT - VD, the resulting termination resistance RL, the capacitive bus load CL and the bit rate. Figure 28 shows the dependence of power dissipation of the transmitter as function of VSUP. The conditions for calculation the power dissipation was: RL = 500 W, CL = 10 nF, Bitrate = 20 kbit and duty cycle on TxD of 50%.
TJ-TA is the temperature difference between junction and ambient, and Rth is the thermal resistance of the package. The thermal energy is transferred via the package and the pins to the ambient. This transfer can be improved with additional ground areas on the PCB as well as ground areas under the IC.
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NCV7361A
Table 1. SO-8 Thermal RC Network Models*
Copper Area (1 oz thick) (SPICE Deck Format) C_C1 C_C2 C_C3 C_C4 C_C5 C_C6 C_C7 C_C8 C_C9 C_C10 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R7 R_R8 R_R9 R_R10 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 Junction node1 node2 node3 node4 node5 node6 node7 node8 node9 GND GND GND GND GND GND GND GND GND GND node1 node2 node3 node4 node5 node6 node7 node8 node9 GND 54 mm2 54 mm2 1.08E-05 4.10E-05 1.13E-04 4.42E-04 1.74E-03 1.39E-03 2.08E-02 1.08E-02 1.14E-01 8.11E-01 0.119 0.286 0.857 1.181 1.241 2.574 18.065 27.965 80.896 49.468 714 mm2 714 mm2 1.08E-05 4.10E-05 1.13E-04 4.40E-04 1.71E-03 1.34E-03 1.78E-02 9.75E-03 1.84E-01 3.00E+00 0.119 0.286 0.859 1.189 1.276 2.690 21.708 26.035 49.821 15.252 Units W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W 54 mm2 Tau 1.00E-06 1.00E-05 1.00E-04 5.00E-04 1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 5.00E+01 R's 0.070 0.152 0.481 0.690 0.584 3.223 0.823 26.801 63.710 86.119 714 mm2 Tau 1.00E-06 1.00E-05 1.00E-04 5.00E-04 1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 5.00E+01 R's 0.070 0.152 0.481 0.690 0.584 3.223 0.823 35.166 52.538 25.510 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Units sec sec sec sec sec sec sec sec sec sec Cauer Network Foster Network
*Bold face items in the tables above represent the package without the external thermal system.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit
Junction R1 R2 R3
simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula:
R(t) +
S1 Ri 1-e-t taui i+
Rn Cn
n
C1
C2
C3
Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values.
Ambient (thermal ground)
Figure 29. Grounded Capacitor Thermal Network ("Cauer" Ladder)
Junction R1 R2 R3 Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC-product time constant; Amplitudes are the resistances
Ambient (thermal ground)
Figure 30. Non-Grounded Capacitor Thermal Ladder ("Foster" Ladder)
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NCV7361A
190 180 170 qJA (C/W) 160 1.0 oz. Cu 150 140 130 120 110 100 0 100 200 300 400 Copper Area (mm2) 500 600 700 800 2.0 oz. Cu
Figure 31. SO-8, qJA as a Function of the Pad Copper Area Including Traces, Board Material
1000 Cu Area = 53.9 mm2 1.0 oz. 100 Cu Area = 89.7 mm2 1.0 oz.
Rq (C/W)
10
Cu Area = 713.9 mm21.0 oz.
1
0.1
0.01 0.000001
0.00001
0.0001
0.001
0.01 Time (s)
0.1
1
10
100
1000
Figure 32. SO-8 Thermal Transient Response on Typical Test Boards
1000 Rq (C/W) EFFECTIVE THERMAL RESISTANCE Cu Area = 713.9 mm21.0 oz. 100 50% Duty Cycle
10% 10 5% 2% Notes: 1 1% 0.1 Single Pulse PDM t1 t2 t1 Duty Cycle, D = t 2 0.0001 0.001 0.01 Time (s) 0.1 1 10 100 1000
0.01 0.000001
0.00001
Figure 33. SO-8 Thermal Duty Cycle Curves on 1.0 in. Spreader Test Board
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NCV7361A
60 maximum current 50 IVCC_max (mA) 40 30 20 10 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSUP (V) SOIC8 TA = 85C TJ = 150C
Input Capacity on VSUP CIN
SOIC8 TA = 125C TJ = 150C SOIC8 TA = 85C TJ = 125C
max. supply voltage
It is necessary to have an input capacity of CIN = 4.7 mF. Higher capacity values improve the line transient response and the supply noise rejection behavior. The combination of electrolytic capacity (e.g.100 mF) in parallel with a ceramic RF-capacity (e.g. 100 nF) archives good disturbance suppressing. The input capacity should be placed as close as possible (< 1 cm) to the VSUP pin.
Load Capacity on VOUT CL
Figure 34. Safe Operating Area
The linear regulator of the NCV7361A operates with input voltages up to 18 V and can output a current of 50 mA. The maximum power dissipation limits the maximum output current at high input voltages and high ambient temperatures. The output current of 50 mA at an ambient temperature of TA = 125C is only possible with small voltage differences between VSUP and VCC. See Figure 34 for safe operating areas for different ambient and junction temperatures. Regulator Circuitry
Low Dropout Regulator
The regulator is stabilized by the output capacitor CL. The NCV7361A requires a minimum of 4.7 mF capacity connected to the 5.0 V output to insure stability. This capacitor should maintain its ESR in the stable region of the ESR curve (Figure 35) over the full operating temperature range of the application. The capacity value and the ESR of a capacitor changes with temperature. The minimal capacity value must be kept within the whole operating temperature range.
Example 1:
The regulator is stabilized using a 47 mF aluminum electrolytic capacitor load (ESR = 0.7 W @ 25C). The capacitance decreases to 42 mF and the ESR increases to 8.9 W at an ambient temperature of -40C. The ESR value is located in the unstable region. The regulator will be unstable at -40C.
Example 2:
The voltage regulator of the NCV7361A is a low dropout regulator (LDO) with a P-MOSFET as the driving transistor. This type of regulator has a standard pole, generated from the internal frequency compensation and an additional pole, which is dependent from the load and the load capacity. This additional pole can cause an instable behavior of the regulator! It requires a zero point to compensate this additional pole. It can be realized via an additional load resistor in series with a load capacity. It is used for this compensation the Equivalent Series Resistance (ESR) of the load capacity. Every real capacity is characterized with an ESR value. With the help of this ESR value an additional zero point is implemented into the amplification loop and therefore the result of the negative phase shift is compensated. Because of this correlation the regulator has a stable operating area which is defined by the load resistance RL, the load capacity CL and the corresponding ESR value. The load resistance resp. load current is defined by the application itself and therefore the compensation of the pole can only be done via variation of the load capacity and ESR value.
The regulator is stabilized using a 47 mF tantalum capacitor load (ESR = 0.1 W @ 25C). The capacitance decreases to 45 mF and the ESR increases to 0.11 W at an ambient temperature of -40C. The ESR value is located in the stable region. The regulator will be stable at -40C.
100
ESR @ 100 kHz (Ohm)
10
Unstable Region
1 Stable Region 0.1 Unstable Region
0.01 0
10
20
30
40
50
Load Current (mA)
Figure 35. ESR Curves for 6.8 mF 3 CL 3 100 mF and Frequency of 100 kHz
The value and type of the output capacitor can be selected by using the diagram shown in Figure 35.
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NCV7361A
Capacity Value
The capacity value of an electrolytic capacitor is dependence from the voltage, temperature and the frequency. The temperature coefficient of the capacity value is positive, that means that the value increases with increasing of the temperature. The capacity value decreases with increasing of the frequency. This behavior of a capacitor can cause that at TA = -40C the capacity value falls below the minimum required capacity for the regulator. In this case the regulator becomes instable, which means the regulator starts oscillation. The nominal value of the capacitor at TA = 25C has to be chosen with enough margin under consideration of the capacitor specification. The instable behavior will be amplified because of the decreasing of the capacity with this oscillation.
ESR
Normally the specified ESR values for a capacitor is valid at a temperature of TA = 25C and a frequency of f = 100 kHz. The temperature coefficient is negative, which means with increasing of the temperature the ESR value decreases. In the choice of the capacity has to be taken into account that the ESR can decrease at TA = -40C dramatically that the valid operating area can be left, which causes that the regulator will be instable.
Tantalum Capacitors
This type of capacitor has a low dependence of the capacity and the ESR from the temperature and is therefore well suitable as VOUT load capacity.
Aluminum Capacitors
The Equivalent Serial Resistance is the resistor part of the equivalent circuit diagram of a capacitor. The ESR value is dependent from the temperature and frequency.
These capacitors show a strong influence of the capacity and the ESR from the temperature. These characteristic restrains the usability as load capacity for the low drop regulator of NCV7361A.
Reverse Protection-Diode VBAT 100 mF + 100 nF
NCV7361A
VSUP EN GND VOUT RESET TxD RxD + 10 mF...100 mF or Optional 100 nF
mC
+5 V
LIN-BUS 220 pF
BUS
10 RC-Filter 100 p
33 mH LC-Filter 82p
Figure 36. Application Circuit (Slave Node) EMI Suppressing
To minimize the influence of EMI from the bus line, a 220 pF capacitor should be directly connected to the BUS pin (see Figure 36). The value of the filter capacity can be adjusted to the size of the LIN network. 220 pF should be used for bigger networks. Values from 333 pF up to 1.0 nF should be used for middle to small LIN networks. Finally the size of the
filter capacitor influences the effectiveness of the EMI suppressing in conformance to the maximum LIN bus capacity of 10 nF. LC-filters or RC-filters can also be used. The value of C, L or R, depends on the corner frequency, the maximum LIN bus capacity (10 nF) and the compliance with the DC- and AC LIN bus parameters.
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NCV7361A
VBAT
+ 100nF
VIN GND
VOUT
+ 100mF 100nF
+5 V
NCV7380*
1k NC VS BUS 220pF GND RxD NC VCC TxD 100nF Master Node LIN-BUS
100nF
mP
NCV7361A
+ 100mF VSUP 1k 100nF 100nF EN GND BUS 220pF + 100mF Slave Node *Not representative of actual pinout. 100nF RESET TxD RxD VOUT +5 V
mC
Figure 37. Application Circuit for LIN Sub-Bus with NCV7361A as Slave Node
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NCV7361A
Connection to Flash-MCU
During programming of a flash MCU the NCV7361A should be disconnected from the MCU. This can be done by disconnecting the supply voltage of the NCV7361A or by turning off the NCV7361A with the EN pin. A blocking
diode must be used between the MCU and the RxD pin to avoid loading of the programming data. The programming of the flash is also possible via the LIN pin, if the MCU supports this kind of flash mode.
Prog.-Data
10mF...47mF
NCV7361A
VOUT 47nF...100nF RESET TxD RxD 0.7 V Vhigh_RxD > 4.7 V at VDD = 5 V Vlow_RxD = 0.8 V Vhigh = 4 V at VDD = 5 V +
mC
Figure 38. Example Circuitry for Connection of RxD to MCU for Flash Programming
Operating During Disturbance
Operating Without VSUP or GND
Short Circuit VOUT to GND
The BUS pin is designed for voltages of GND - 24 V up to GND + 30 V. This prevents loss of communication between other bus nodes with the loss of VSUP or loss of GND. The BUS pin will remain at VBAT and current draw will be minimal with the loss of GND or VSUP.
Short Circuit BUS to VBAT
The VOUT pin is protected via a current limit. This state is comparable with the behavior in the sleep mode.
Overload of VOUT
Thermal Switch-Off
* Recessive
* Dominant
LIN bus is blocked, no influence to the NCV7361A Current limit, thermal shutdown of NCV7361A if power dissipation raises TJ
The power dissipation is increasing if the load current is between IVOUT_max and ILVOUT. If the IC exceeds the thermal shutdown threshold of > 155C, the transceiver will be switched off. The voltage regulator will also be switched off and a reset signal is forced.
Overcurrent
Short Circuit BUS to GND
The LIN bus is blocked. There is no influence to the NCV7361A.
Short Circuit TxD to GND
If the current limit is active the voltage on VOUT drops down. If this voltage is below the threshold VRES, a reset will be forced.
Undervoltage VSUP, VOUT
The LIN transceiver is permanent in the dominant state as is the LIN bus. This state can only be detected from the LIN controller. In this case the controller must switch-off the LIN node via the EN input of the NCV7361A and look for a recessive state. A thermal shutdown of NCV7361A will appear if the thermal shutdown threshold is exceeded.
TxD Open
The reset circuit guarantees the correct behavior of the driver during undervoltage. The BUS pin generates the recessive state if VOUT < VMRes. The inputs EN and TxD have pull-down and pull-up circuits respectively. If VMRes v VOUT v 4.5 V the TxD signal is transmitted to the bus. The receive mode is also active.
Short Circuit RxD, RESET to GND or VOUT
Both outputs are short circuit proof to VOUT and ground.
The internal pullup resistor forces the LIN node to the recessive state. The communication between the other bus-nodes will not be disturbed.
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NCV7361A
ESD/EMC Remarks
General Remarks ESD Test
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
The NCV7361A is tested according to MIL883-3015.7 (Human Body Model).
EMC
The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for data and signal pins.
POWER SUPPLY PIN VSUP
Test Pulse 1 2 3a/b 5 Condition t1 = 5.0 s/US = -100 V/tD = 2.0 ms t1 = 0.5 s/US = 100 V/tD = 0.05 ms US = -150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Ri = 0.5 W, tD = 400 ms tr = 0.1 ms/UP + US = 40 V Duration 5000 Pulses 5000 Pulses 1h 10 Pulses Every 1 Min
DATA AND SIGNAL PINS EN, BUS
Test Pulse 1 2 3a/b Condition t1 = 5.0 s/US = -100 V/tD = 2.0 ms t1 = 0.5 s/US = 100 V/tD = 0.05 ms US = -150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break Duration 1000 Pulses 1000 Pulses 1000 Burst
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NCV7361A
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AE
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
RECOMMENDED FOOTPRINT
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
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NCV7361A
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